
@INPROCEEDINGS{chisel:dac2012,
  author = {Jonathan Bachrach and Huy Vo and Brian Richards and Yunsup Lee and
        Andrew Waterman and Rimas Avizienis and John Wawrzynek and Krste
        Asanovic},
  title = {Chisel: constructing hardware in a {Scala} embedded language},
  booktitle = {The 49th Annual Design Automation Conference (DAC 2012)},
  year = {2012},
  editor = {Patrick Groeneveld and Donatella Sciuto and Soha Hassoun},
  pages = {1216--1225},
  address = {San Francisco, {CA}, {USA}},
  month = {June},
  publisher = {ACM},
  bibdate = {2012-06-01},
  bibsource = {DBLP, http://dblp.uni-trier.de/db/conf/dac/dac2012.html#BachrachVRLWAWA12},
  isbn = {978-1-4503-1199-1},
  url = {http://dl.acm.org/citation.cfm?id=2228360}
}

@ARTICLE{patmos:rts2018,
  author = {Martin Schoeberl and Wolfgang Puffitsch and Stefan Hepp and Benedikt
	Huber and Daniel Prokesch},
  title = {Patmos: A Time-predictable Microprocessor},
  journal = {Real-Time Systems},
  year = {2018},
  volume = {54(2)},
  pages = {389--423},
  month = {Apr},
  doi = {10.1007/s11241-018-9300-4},
  issn = {1573-1383}
}

@BOOK{Scala,
  title = {Programming in Scala, 3rd Edition},
  publisher = {Artima Inc},
  year = {2016},
  author = {Bill Venners and Lex Spoon and Martin Odersky},
  owner = {martin},
  timestamp = {2017.11.15}
}

@INPROCEEDINGS{lipsi:arcs2018,
  author = {Martin Schoeberl},
  title = {Lipsi: Probably the Smallest Processor in the World},
  booktitle = {Architecture of Computing Systems -- ARCS 2018},
  year = {2018},
  pages = {18--30},
  publisher = {Springer International Publishing},
  doi = {10.1007/978-3-319-77610-1_2},
  isbn = {978-3-319-77610-1},
  url = {https://www.jopdesign.com/doc/lipsi.pdf}
}

@INPROCEEDINGS{leros:arcs2019,
  author = {Martin Schoeberl and Petersen, {Morten Borup}},
  title = {Leros: The return of the accumulator machine},
  booktitle = {Architecture of Computing Systems - ARCS 2019 - 32nd International
	Conference, Proceedings},
  year = {2019},
  editor = {Martin Schoeberl and Thilo Pionteck and Sascha Uhrig and J{\"u}rgen
	Brehm and Christian Hochberger},
  pages = {115--127},
  month = {1},
  publisher = {Springer},
  day = {1},
  doi = {10.1007/978-3-030-18656-2_9},
  isbn = {9783030186555},
  language = {English}
}

@BOOK{dally:vhdl:2016,
  title = {Digital design using VHDL: A systems approach},
  publisher = {Cambridge University Press},
  year = {2016},
  author = {William J. Dally and R. Curtis Harting and Tor M. Aamodt},
  pages = {664}
}

@techreport{rocket:techrep,
    Author = {Asanović, Krste and Avizienis, Rimas and Bachrach, Jonathan and Beamer, Scott and Biancolin, David and Celio, Christopher and Cook, Henry and Dabbelt, Daniel and Hauser, John and Izraelevitz, Adam and Karandikar, Sagar and Keller, Ben and Kim, Donggyu and Koenig, John and Lee, Yunsup and Love, Eric and Maas, Martin and Magyar, Albert and Mao, Howard and Moreto, Miquel and Ou, Albert and Patterson, David A. and Richards, Brian and Schmidt, Colin and Twigg, Stephen and Vo, Huy and Waterman, Andrew},
    Title = {The Rocket Chip Generator},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {2016},
    Month = {Apr},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html},
    Number = {UCB/EECS-2016-17},
    Abstract = {Rocket Chip is an open-source Sysem-on-Chip design generator that emits synthesizable RTL. It leverages the Chisel hardware construction language to compose a library of sophisticated generators for cores, caches, and interconnects into an integrated SoC. Rocket Chip generates general-purpose processor cores that use the open RISC-V ISA, and provides both an in-order core generator (Rocket) and an out-of-order core generator (BOOM). For SoC designers interested in utilizing heterogeneous specialization for added efficiency gains, Rocket Chip supports the integration of custom accelerators in the form of instruction set extensions, coprocessors, or fully independent novel cores. Rocket Chip has been taped out (manufactured) eleven times, and yielded functional silicon prototypes capable of booting Linux.}
}

@INPROCEEDINGS{s4nocni:arcs2019,
  author = {Martin Schoeberl and Luca Pezzarossa and Jens Spars{\o}},
  title = {A minimal network interface for a simple network-on-chip},
  booktitle = {Architecture of Computing Systems - ARCS 2019},
  year = {2019},
  editor = {Martin Schoeberl and Thilo Pionteck and Sascha Uhrig and J{\"u}rgen
	Brehm and Christian Hochberger},
  pages = {295--307},
  month = {1},
  publisher = {Springer},
  day = {1},
  doi = {10.1007/978-3-030-18656-2\_22},
  isbn = {9783030186555},
  language = {English}
}

@INPROCEEDINGS{t-crest:memnoc,
  author = {Martin Schoeberl and David VH Chong and Wolfgang Puffitsch and Jens
	Spars{\o}},
  title = {A Time-predictable Memory Network-on-Chip},
  booktitle = {Proceedings of the 14th International Workshop on Worst-Case Execution
	Time Analysis (WCET 2014)},
  year = {2014},
  pages = {53--62},
  address = {Madrid, Spain},
  month = {July},
  doi = {10.4230/OASIcs.WCET.2014.53},
  url = {http://www.jopdesign.com/doc/memnoc.pdf}
}

@INPROCEEDINGS{t-crest:ownspm,
  author = {Martin Schoeberl and T{\'o}rur Biskopst{\o} Str{\o}m and Oktay Baris
	and Jens Spars\o{}},
  title = {Scratchpad Memories with Ownership},
  booktitle = {2019 Design, Automation and Test in Europe Conference Exhibition
	(DATE)},
  year = {2019}
}

@TECHREPORT{risc-v,
  author = {Waterman, Andrew and Lee, Yunsup and Patterson, David A. and Asanovic,
        Krste},
  title = {The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA},
  institution = {EECS Department, University of California, Berkeley},
  year = {2011},
  number = {UCB/EECS-2011-62},
  month = {May},
  url = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.html}
}

@PHDTHESIS{Zimmer:EECS-2015-181,
  author = {Zimmer, Michael},
  title = {Predictable Processors for Mixed-Criticality Systems and Precision-Timed
        I/O},
  school = {EECS Department, University of California, Berkeley},
  year = {2015},
  month = {Aug},
  number = {UCB/EECS-2015-181},
  url = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-181.html}
}

@INPROCEEDINGS{OpenSoC:ispass2016,
  author = {Farzaf Fatollahi-Fard and David Donofrio and George Michelogiannakis
	and John Shalf},
  title = {OpenSoC Fabric: On-chip network generator},
  booktitle = {2016 IEEE International Symposium on Performance Analysis of Systems
	and Software (ISPASS)},
  year = {2016},
  pages = {194--203},
  month = {April},
  doi = {10.1109/ISPASS.2016.7482094}
}

@INPROCEEDINGS{RoCC:2015,
author={Schuyler Eldridge and Amos Waterland and Margo Seltzer and Jonathan Appavooand Ajay Joshi},
booktitle={2015 International Conference on Parallel Architecture and Compilation (PACT)},
title={Towards General-Purpose Neural Network Computing},
year={2015},
volume={},
number={},
pages={99--112},
keywords={feedforward neural nets;learning (artificial intelligence);neural net architecture;recurrent neural nets;general-purpose neural network computing;machine learning;hardware accelerator;software-hardware extension;power consumption;X-FILES;feedforward neural network;feedback neural network;neural network accelerator architecture;DANA;Artificial neural networks;Hardware;Software;Registers;Standards;Accelerator architectures},
doi={10.1109/PACT.2015.21},
ISSN={1089-795X},
month={Oct},}


